The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
A phase locked loop (PLL) based clock generator generates a clock signal with reference to an oscillation signal having a relatively stable frequency, such as an oscillation signal generated by a crystal oscillator external to an integrated circuit (IC) chip. Thus, the frequency of the clock signal is stable and does not vary with process, voltage, and temperature changes of the IC chip.